1. Field of the Invention
The present invention relates to a solid state imaging apparatus, in particular, to a CMOS image sensor, which varies a readout voltage of signal charges in accordance with potential levels related to a photodiode.
2. Description of Related Art
Solid state photoelectrical converters, that is, semiconductor light image sensors, are roughly classified into two categories; CCD image sensors and CMOS image sensors. The CCD image sensors are actually widely put into practical use. However, a photoelectrical conversion section (pixel section) of the CCD image sensor and a peripheral circuit section thereof are fabricated using different procedures. On the other hand, a pixel section and a peripheral circuit section of the CMOS image sensor can be fabricated using almost the same procedure as that of a normal CMOS process, and can be incorporated into the same substrate when manufacturing the CMOS image sensor.
The pixel section of the CMOS image sensor includes a plurality of unit pixels arranged in the form of a matrix. Each of the unit pixels includes, as shown in FIG. 1A, a photodiode 64 and a readout transistor 65 configured to read out signal charges accumulated in the photodiode 64. A gate voltage generator 76 is connected to a gate electrode of the readout transistor 65. A select switch 74 switches a voltage applied to the gate electrode so as to turn on and off the readout transistor 65. A power supply 90 generating a constant power supply voltage Vd is configured to be connected to the ON (High) side of the select switch 74, whereas a ground potential is applied to the OFF (Low) side of the select switch 74.
As shown in FIG. 1B, a gate electrode 92 is placed on a silicon substrate 77 with a gate insulating film 91 therebetween. A buried photodiode 64 is placed at left side of the gate electrode 92. As shown in FIG. 1C, when a ground potential is applied to the gate electrode 92, a potential under the gate electrode 92 decreases to a channel potential (Low) cpa. In FIGS. 1C and 1D, the potential is measured in a downward direction. Signal charges 75a generated by the photodiode 64 are confined above a depletion potential dp of the photodiode 64 by a potential barrier having a barrier height of cpa-dp. When the power supply voltage Vd is applied to the gate electrode 92, a potential under the gate electrode 92 increases to a channel potential (High) cpb. As a result, the potential barrier is eliminated, and therefore, the confined signal charges 75a pass through the channel under the gate electrode 92 to be read out selectively.
By maintaining the relation of dp<cpb in the readout operation of the signal charges, all the signal charges can be read out. Accordingly, an after-image phenomenon due to the remaining signal charges after readout does not occur. If a channel potential (High) cpb′ becomes lower than the depletion potential dp, the potential barrier remains in the channel under the gate electrode 92 as shown in FIG. 1D. Therefore, a part of signal charge 75b remains in the photodiode 64 after readout, resulting in deterioration of after-image characteristics of the CMOS image sensor.
Therefore, the power supply voltage Vd is set higher than actually needed with respect to the depletion potential dp so that the relation of dp<cpb is always maintained, even if variation in fabrication occurs in the depletion potential dp.
However, when the power supply voltage Vd to be applied to the gate electrode 92 is set high, the breakdown voltage of the gate insulating film 91 is deteriorated. Therefore, DC failures are likely to occur. More specifically, since the power supply voltage Vd applied to the gate electrode 92 of the transistor 65 is set higher than necessary in order to prevent the deterioration of the after-image characteristics, the probability of occurrence of DC failures increases.